1. Field of the Invention
The present invention relates to the manufacture of integrated circuits and, in particular, to a method and system for determining overlay error in lithographic processing of integrated circuits.
2. Description of Related Art
Semiconductor manufacturing requires the sequential patterning of process layers on a single semiconductor wafer. Lithographic exposure tools known as steppers or scanners print multiple integrated circuit patterns or fields by lithographic methods on successive layers of the wafer. These exposure tools typically pattern different layers by applying step and repeat lithographic exposure or step and scan lithographic exposure in which the full area of the wafer is patterned by sequential exposure of the stepper fields containing one or more integrated circuits. Typically, 20-50 layers are required to create an integrated circuit.
In order to match corresponding features in successive lithographic process layers on the semiconductor wafer, it is important to keep overlay error as small as possible and within predetermined limits. Measurements are typically performed using metrology imaging tools, such as optical, scanning e-beam or atomic force microscopy systems. Prior art calibration artifacts and methods include box-in-box (BiB) or one dimensional (1-D) grating overlay patterns.
U.S. application Ser. Nos. 11/162,506 and 11/833,304, the disclosures of which are hereby incorporated by reference, disclose improved methods and target systems for determining overlay or alignment error between different fields in the same lithographic level or among the many lithographic levels required to create an integrated circuit. The multi-layer overlay target disclosed therein achieves comparable or superior metrology performance to box-in-box or grating structures, at substantial reduction of metrology target real estate.
Semiconductor overlay is routinely controlled using post lithography optical metrology, i.e., after development of the resist layer on which the images are projected. The overlay errors are collected from the metrology imaging tool and input into an automated process control (APC) application that models the linear error terms and feeds back optimized settings for lot-to-lot control. This control method provides fast feedback response since the lot is measured immediately after the imaging step.
FIG. 1 illustrates a prior art method of post-develop overlay metrology. Layer M of the current wafer lot L is deposited 120 over the previously etched and completed lithographic process layer M−1. At this Mth process level, the mask and projected image are aligned 122 over the layer to be etched. The image of the Mth layer is then exposed and developed 124 on a resist layer over layer M, and the exposure and development alignment settings A are stored in control database 134. To monitor overlay quality and feed back corrections to the alignment settings of the current lot L, the corrections are based on the weighted average of the actual alignment settings Ai minus the corresponding modeled errors Di in control database 134, which are based on post-develop overlay metrology 126 of prior lots i<L. Feedback correction CL to the alignment settings of the current lot L is computed 36 as follows:
            C      L        =                  ∑                  i          =          1                          L          -          1                    ⁢                        w          i                ⁡                  (                                    A              i                        -                          D              i                                )                                        ∑                  i          =          1                          L          -          1                    ⁢              w        i              =    1  
In general, C, A, and D are vectors representing the set of alignment terms applicable to a given lithography system.
However, a drawback to using post lithography data is that the measurements can be readily biased by previous processing of the wafers. It has been found that specific process layers are susceptible to process-induced shifts in the post-develop overlay measurements relative to the true overlay; e.g. chemical-mechanical polishing (CMP) smearing of overlay marks, asymmetric mark fill, asymmetric resist coating, and the like. This bias, which frequently fits the modeled parameters, is then fed back to the lithography tool on subsequent lots resulting in an alignment error. The error is self-fulfilling to lot disposition in that the resulting lot overlay measurements appear to be in specification. This error may go unnoticed until final wafer test where the result may be yield loss. Thus, it would be desirable to include the results of post-etch overlay metrology in the determination of the optimum post-alignment corrections C.
Measuring the overlay targets after the final image, or post etch processing, can result in more accurate measurements. Post lithography processing frequently removes the optical error bias. In this way, it would be better to disposition the lot and control the lithography process by measuring the lot overlay after the post lithography processing. As shown in FIG. 1, etch overlay feedback requires insertion of a post-etch overlay metrology step 130, after etching the developed pattern 128. However, this is not believed to be done in the industry for three reasons: 1) the lot cannot be reworked once it has gone through further processing; 2) the feedback response time for lot to lot control is greatly lengthened; and 3) since the lot must be measured post litho for the rework issue, post etch metrology adds to both wafer cost and requires extra tool capacity. This makes the post etch measurement generally too costly to implement in addition to the post lithography measurement.